High-Performance ASIC SPI Master Controller (TSMC 180nm)

Summary

This VLSI digital design project encompasses the complete RTL design, verification, and physical layout of a high-performance Serial Peripheral Interface (SPI) Master Controller. Specifically targeting the TSMC 180nm process node, the controller is engineered to serve as a highly efficient, full-duplex communication bridge for a System-on-Chip (SoC).

To maximize throughput and decouple the main CPU from slow serial transactions, the architecture integrates dedicated hardware FIFO buffers and independent slave management logic. Furthermore, the design underwent rigorous Power, Performance, and Area (PPA) optimization to ensure viability for modern, ultra-low-power embedded systems.

Technical Implementation & Architecture

I architected the controller using a highly modular Verilog framework, dividing the system into three primary subsystems to ensure scalability and robust verification:

• Asynchronous CPU Offloading: Implemented a 4-entry First-In First-Out (FIFO) buffer system (handling both 32-bit data and 2-bit Chip Select signals). The CPU can burst data into the buffer in a single clock cycle, allowing the SPI Finite State Machine (FSM) to autonomously manage the serial transmission without stalling the processor.
• Universal Protocol Support: Engineered a configurable serial clock generator and FSM that natively supports all four standard SPI modes via dynamic Clock Polarity (CPOL) and Clock Phase (CPHA) inputs, alongside dedicated hardware routing for up to four independent slave devices.
• Physical Layout & Synthesis: Verified behavioral logic using AMD Vivado, then transitioned to Cadence RTL Compiler for synthesis. The final physical layout and routing were successfully generated using Cadence Innovus.

Technologies I used for this project

Main Technologies

• Verilog (RTL Design)
• VLSI System Design
• Power, Performance, and Area (PPA) Optimization

ASIC & Tooling

• Cadence RTL Compiler (Synthesis)
• Cadence Innovus (Physical Layout)
• TSMC 180nm CMOS Technology Library
• AMD Vivado (Behavioral Simulation)

Synthesis Results & Power Optimization

During synthesis, initial analysis revealed that the FIFO buffers accounted for nearly 48% of the total energy consumption due to continuous clock switching activity. Because typical SPI peripherals operate between 10–50 MHz, the initial Fmax of 285.5 MHz was unnecessarily high for most SoC applications.

To dramatically improve the power profile, I applied automated Integrated Clock Gating (ICG) to replace multiplexer-based loops. This physical-level optimization yielded massive efficiency gains:

• Total Power Consumption: Reduced from 0.77 mW to 0.37 mW (52.2% Reduction).
• FIFO Power Drain: Plunged from 0.37 mW to 0.10 mW (72.7% Reduction).
• Total Silicon Area: Shrunk by 15.4% down to 23,425 um^2, while still easily meeting target frequency requirements at 224.7 MHz.