Bare-Metal SPI Driver for MSP430FR6989

Summary

This hardware-level software project features a high-performance, bare-metal Serial Peripheral Interface (SPI) driver engineered for the Texas Instruments MSP430FR6989 microcontroller.

The objective was to create a lightweight, low-overhead API for interfacing with external peripherals (such as sensors and displays) by completely bypassing heavy Hardware Abstraction Layers (HALs). By directly manipulating the microcontroller's eUSCI hardware registers, this driver achieves extremely fast, synchronous, full-duplex communication with a minimal memory footprint.

Technical Implementation & Architecture I architected the driver to cleanly abstract the complexities of the eUSCI (Enhanced Universal Serial Communication Interface) module while maintaining absolute control over the physical bus characteristics. The initialization sequence manually controls the software reset state, configures the bit clock prescalers via the internal Sub-Main Clock (SMCLK), and routes the hardware signals to the appropriate GPIO pins.

Key engineering highlights include:

Advanced Clock Configuration: Engineered full support for configuring Clock Polarity (CPOL) and Clock Phase (CPHA) via direct register bit-masking. This ensures absolute compatibility across all four standard SPI modes required by various external ICs.
Master Bus Control: Configured the microcontroller to operate exclusively in Master mode, securely generating the serial clock (SCLK) and driving the Master-Out-Slave-In (MOSI) data line.
Direct Register Manipulation: Managed all MSB-first formatting, synchronous mode enabling, and transmit/receive buffer handling natively in C without relying on external RTOS dependencies.

Technologies I used for this project

Main Technologies

Embedded C
Bare-metal execution (No RTOS/HAL)
Hardware-Software Abstraction

Hardware & Protocols

TI MSP430FR6989 Microcontroller
SPI Protocol (Synchronous Serial)
eUSCI Hardware Module

Tools & Environments

Code Composer Studio (CCS)
TI C/C++ Compiler
Logic Analyzers / Oscilloscopes

Results

This project highlights a deep understanding of synchronous serial bus architecture and physical-layer timing requirements. The resulting driver provides a highly stable, modular foundation for integrating complex external hardware into resource-constrained embedded systems.