Synthesizable UART Module in SystemVerilog

Summary

This digital logic design project features a fully synthesizable Universal Asynchronous Receiver-Transmitter (UART) module written in SystemVerilog. Engineered to serve as a foundational building block for larger System-on-a-Chip (SoC) architectures, this module provides a standard, byte-oriented serial communication interface.

The design strictly adheres to a standard 8-N-1 frame format (1 Start Bit, 8 Data Bits, No Parity, 1 Stop Bit) and features full-duplex communication, allowing for simultaneous data transmission and reception. It is fully parameterized, allowing the baud rate to be dynamically generated from any system clock frequency.

Technical Implementation & Architecture The architecture was developed using a clean, highly modular approach in AMD Vivado, ensuring seamless synthesis for Field-Programmable Gate Arrays (FPGAs), specifically targeting the Digilent Nexys A7-100T.

The top-level wrapper (uart_top.sv) instantiates three distinct core components:

Baud Rate Generator (baud_rate_generator.sv): Utilizes a precise counter and parameterized divisor logic derived from the system clock to generate a periodic clock enable signal.
UART Receiver (uart_rx.sv): Implements a robust oversampling mechanism. It continually polls the incoming serial line (rx_in) to detect the start bit, then deliberately samples the geometric center of each subsequent data bit to deserialize the byte, mitigating potential clock drift or signal noise.
UART Transmitter (uart_tx.sv): Manages the parallel-to-serial conversion, framing loaded bytes into standard UART packets and transmitting them bit-by-bit on the tx_out line at the strictly enforced baud rate.

Technologies I used for this project

Main Technologies

SystemVerilog (HDL)
Digital Logic Design
RTL (Register-Transfer Level) Synthesis

Hardware & Tooling

Digilent Nexys A7-100T (FPGA)
AMD Vivado ML Edition
Simulation Waveforms

Next Steps: Advanced Verification & Hardware

Loopback With basic behavioral simulation successfully verified, the project is currently advancing into professional-grade Design Verification (DV). Future milestones include building a comprehensive verification environment utilizing the Universal Verification Methodology (UVM) to perform constrained-random testing, functional coverage analysis, and scoreboard validation.